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Why are existing power analysis flows and methodologies falling short and what's the solution?


POWER - USAGE SHIFT LEADS TO METHODOLOGY SHIFT
   
Hello
electronic!



VIJAY CHOBISA, PRODUCT MARKETING MANAGER, MENTOR GRAPHICS
GAURAV SAHARAWAT, STAFF ENGINEER RUNTIME R&D, MENTOR GRAPHICS



CHALLENGE

Why has power suddenly become a high visibility topic? One reason is that power
exploration and accurate power calculation of SoCs in the target application environment is getting executive attention due to the fact that companies are missing market windows because of power issues. Power issues are caused because of a usage shift in mobile computing devices (phones, tablets, etc.).  These devices are now being used for playing games, watching movies or NFL or NBA games in addition to typical cell phone usage.  This usage shift warrants a methodology shift in the power analysis flow.  Why are existing power analysis flows and methodologies falling short? First, FINFET is a technology that helps reduce static power, but dynamic power is still the largest power consumer as chips are getting faster and the screens in today's mobile devices are being produced with much higher resolution. Second, adapted functional testbenches, traditionally used for power number generation, are not adequate for analyzing power problems. Finally, power analysis tools are not designed to do power measurements at the full chip/system level while running live software applications. Indeed, power analysis is becoming equally or more important as functional verification for today's power hungry SoCs.

To view figure 1 along with full white paper: click here

FUNCTIONAL TESTBENCH VS. LIVE APPLICATION 
If you look at existing flows for power measurement, you quickly realize that chip designers are making lots of assumptions when it comes to generating power numbers for SoCs. They run simulations of functional tests at the block or subsystem level, generating switching activity in the form of Switching Activity Interchange Format (SAIF), FSDB or VCD for a limited number (10s of 1000s) of cycles. Then they supply this data to power analysis tools with a technology library for power number generation. Once they have the power numbers from these adapted functional tests, extrapolation techniques are used to come up with a power number for the full SoC. However, many times these extrapolated power numbers are quite off from real power numbers measured once the chips are back in the lab.

Over the last year, Mentor Graphics has worked with leading fabless chip design companies to establish an emulation flow to generate accurate power numbers. We do this by measuring power in a targeted application environment while running actual software applications. This includes booting an OS and then running hundreds of millions of cycles to locate areas of concern when it comes to power. The Veloce emulation system not only has capacity to handle very large SoCs (up to 2 billion ASIC gates), but also has the performance required to boot an OS, run real applications and generate switching data. In addition, Veloce provides complete visibility of every design node, a must-have capability for accurate power analysis. We believe it's clear that, when it comes to generating the most accurate power number, it's best to use the platform and methodology that allows for analyzing power of an SoC in targeted application environment at the system level. Figure 2 illustrates the need for analyzing power while running live SW applications.

To view Figure 2 along with the full white paper: click here

TRADITIONAL FILE-BASED FLOW
For a traditional file-based flow, Veloce is used to generate switching activity (SAIF) over long emulation run. The data is then used as an input to power analysis tools for generating average power numbers. SAIF-based flows are quite common among customers to do average power estimation; however such flows do not have temporal dependency information as they do not store the full, time-based waveform for all design states. This gap can impact the accuracy of average power for memories or IP, where the calculation is generally more complicated than just considering cumulative switching. Many times it is important to know what portion of activity has occurred during the period its Key ENABLE signals are asserted for improved accuracy of average power

To facilitate the capture of this conditional and segmented switching, Veloce supports the more elaborate version of SAIF known as "Forward SAIF," which can capture all the interesting conditions for switching activity. This is in principle a State and Path Dependent (SDPD) SAIF File for all library cells ports in addition to normal SAIF activity for all design nodes, which improves the accuracy of the average power. However, the accuracy still depends upon the user-supplied Forward SAIF, which is time consuming and difficult to capture as it requires in-depth knowledge of the design.  
 
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