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How interaction is possible between the HDL and HVL domains?


From Simulation To Emulation -
A Fully Reusable UVM Framework
   
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NTRODUCTION
According to the 2012 functional verification study done by the Wilson Research Group, more than half of total ASIC and FPGA development time is spent in verification, justifiably so. Design bugs, if not isolated and fixed at an early stage, get very tricky and exponentially costlier to resolve later. It is therefore critical to ensure that the verification process is complete; in that it has covered as many scenarios as possible before tape out. This contrasts with the technological advances in the wider semiconductor ecosystem, which are shrinking the time available to bring out a chip in the market. Figure 1 shows the average time spent by engineers in various tasks during the verification process.

To view figure 1 along with full white paper: click here

For signoff, it is important that all the tests in the verification plan are complete and pass, hitting the right coveragemetrics. To speed up this verification process, we need both of the following:

- Maximum reuse to reduce the development time for the tests

- Faster verification to reduce the time and effort required for running the tests, debug, and iterations

In the last few years, the industry has converged on UV M (Universal Verification Methodology) as the standard verification methodology, which enables both horizontal (design to design) and vertical (block to subsystem to full chip) reuse. With the entire semiconductor industry getting behind one universal methodology, verification IP developers must also ship UVM compatible components. The rapid adoption of UVM is a testimony of the significant needs it is able to address.

However, adopting the UVM does not address the other significant verification need: the ability to run, debug, and collect metrics for a large number of tests in a short amount of time. This directly correlates to how fast each test can be run, along with, of course, the technology and the tool used. 
 
During the verification process, engineers typically use a variety of tools. They use logic simulators for block-level verification, which traditionally simulate at 10-1000 clock cycles per second. However, the performance of logic simulators goes down drastically with increased design size, rendering them practically impossible to use for system-level integration testing. Simulation speed is also limited by the number of clock cycles required to run a design; for example, a full video frame in even a moderately sized design will take many, many clock cycles and thus a long time to run in pure software simulation.

Emulators aim to fill this gap. By mimicking the actual hard ware in an emulator it can be run at a few million clock cycles per second. Transaction-based acceleration (otherwise known as simulation acceleration) is a special use mode of emulation, where the RTL design in the emulator can interact with a testbench running on a workstation. Interest in this mode has grown rapidly in the past few years and has played a significant role in making emulation easier to use and adopt. Designs which need to run millions of clock cycles to attain full coverage closure or to measure performance metrics are now using emulation even at block level.

It is imperative that the paradigm of reuse enabled by UVM must continue to be facilitated in the context of emulation. This document describes a methodology for writing UVM testbenches that can be used not only for software simulation but also for hardware-assisted acceleration. The methodology derives from the principles of emulation, which, in the context of reusable verification methodology, should give the following benefits: 

Interoperability: Users should be able to run the same environment both in pure simulation and in emulation. There should not be a separate codebase for simulation versus emulation. The methodology, once adapted for emulation, should continue to work.

Flexibility: SystemVerilog has emerged as the most popular verification language. The main benefit of this language is the ability to create dynamic testbenches using the object oriented design paradigm. This language (as well as UVM) provides advanced non-synthesizable features such as constraint random stimulus, functional coverage, SystemVerilog classes which enables configurable sequences, etc., which makes the task of architecting a verification environment much easier. The methodology for emulation must continue to use theseelements in the testbench.

Performance: Users must get the best possible performance with this model. Performance should justify the adoption of this methodology and must be a few orders of magnitude faster than pure software simulation.

When a testbench is architected for emulation, there are essentially two components in a UVM testbench model:

- An HDL static component - which includes the DUT - runs on the emulator at full emulation clock speed

-The HVL dynamic testbench - the behavioral portion - which runs on the workstation simulator

The two are completely independent and separate domains. However, interaction is possible between the HDL and HVLdomains, and performance can be maximized with infrequent interactions between the two. One of the most optimalapproaches is that of remote procedure calls - functions defined in HDL can be called from HVL and vice versa. 
 
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